The present invention relates to an ion implantation apparatus and method for fabrication of a semiconductor device, and more particularly, to an apparatus and method for partial ion implantation using atom vibrations.
In general, a plurality of unit processes must be performed to fabricate a semiconductor device, for example, a semiconductor memory device such as a dynamic random access memory (DRAM). Examples of the unit processes include a stacking process, an etching process, and an ion implantation process, which are performed on a wafer-by-wafer basis. The ion implantation process uses a strong electric field to accelerate dopant ions, such as boron and arsenic, to penetrate a wafer surface, thereby changing the electrical characteristics of the material.
In general, ions are implanted into a wafer by scanning an ion beam in the X-direction while moving the wafer in the Y-direction. However, when ion implantation is performed in the above manner, ions are implanted at about the same dose and energy throughout the entire region of a wafer. This is desirable when considered in terms of only an ion implantation process, but it is undesirable when considered in conjunction with other unit processes. That is, in performing several unit processes on a wafer, the process results are not uniform over the entire area of the wafer. For example, the etching degree and the thickness of a layer stacked on the wafer are not uniform over the entire wafer area. This may be not only because of the problem in the equipment for performing each unit process, but also because many parameters of each unit process cannot be accurately controlled.
As an example, in forming a gate electrode, a critical dimension (CD) representing the width of the gate electrode may differ depending on the locations in a wafer. For example, the CD of the gate electrode may be relatively large at the center of the wafer but relatively small at the edge of the wafer, and vise versa. If the CD of the gate electrode is larger at the center of the wafer than at the edge of the wafer, the threshold voltage of the device is higher at the center of the wafer than at the edge of the wafer. On the other hand, if the CD of the gate electrode is smaller at the center of the wafer than at the edge of the wafer, the threshold voltage of the device is lower at the center of the wafer than at the edge of the wafer.
As another example, in order to form a source/drain region of a lightly doped drain (LDD) structure, a spacer is formed on the side of a gate stack and then source/drain ion implantation is performed using the spacer as an ion implantation barrier layer. However, the thickness of the spacer cannot be uniform over the entire area of a wafer. Therefore, the LDD source/drain region has a profile non-uniform over the entire wafer surface, so that the characteristics of the resulting transistor are non-uniform depending on the locations in the wafer.